Selective Harmonic Mitigation Technique for High-Power Converters

In high-power applications, the maximum switching frequency is limited due to thermal losses. This leads to highly distorted output waveforms. In such applications, it is necessary to filter the output waveforms using bulky passive filtering systems. The recently presented selective harmonic mitigation pulsewidth modulation (SHMPWM) technique produces output waveforms where the harmonic distortion is limited, fulfilling specific grid codes when the number of switching angles is high enough. The related technique has been previously presented using a switching frequency that is equal to 750 Hz. In this paper, a special implementation of the SHMPWM technique optimized for very low switching frequency is studied. Experimental results obtained applying SHMPWM to a three-level neutral-point-clamped converter using a switching frequency that is equal to 350 Hz are presented. The obtained results show that the SHMPWM technique improves the results of previous selective harmonic elimination pulsewidth modulation techniques for very low switching frequencies. This fact highlights that the SHMPWM technique is very useful in high-power applications, leading its use to an important reduction of the bulky and expensive filtering elements.Ministerio de Ciencia y Tecnología TEC2006-03863Junta de Andalucía EXC/2005/TIC-117

Implementation of a closed loop SHMPWM technique for three level converters

High power converters are built using high-voltage and high-current rated semiconductors. The commutation of these devices imply large amounts of energy per cycle leading to very low switching frequency in order to avoid a high rise on the semiconductors temperature. The consequence is high harmonic distortion generated by the converter. Grid codes requirements specify the maximum admitted harmonic distortion. The well-known selective harmonic elimination pulse width modulation (SHEPWM) technique has proved to be useful in eliminating some of the undesired harmonics without increasing the switching frequency, leaving the rest of them free. The solution to the rest of harmonics is to add bulky and expensive filters. Recently, the method named selective harmonic mitigation pulse width modulation (SHMPWM) has been introduced. The aim of this technique is to mitigate the amplitude of the undesirable harmonics, to acceptable values to meet the grid code, considering a larger number of harmonics. In this paper a practical implementation of this technique in a closed loop scheme is presented. The experimental results using a 150 kW three-level diode-champed converter show that the output signals meet the EN 50160 and CIGRE WG 36-05 grid codes. Comparisons between SHMPWM and SHEPWM are included in the experiments, showing the superior performances of the SHMPWM technique

Selective Harmonic Mitigation Technique for Cascaded H-Bridge Converters With Nonequal DC Link Voltages

Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high power applications. A Cascaded HBridge converter is a multilevel topology which is formed from the series connection of H-Bridge cells. Optimized pulse width modulation techniques such as Selective Harmonic Elimination (SHE-PWM) or Selective Harmonic Mitigation (SHM-PWM) are capable of pre-programming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may however not perform optimally if the DC links of the Cascaded H-Bridge Converter are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under non-equal DC link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method

Radiation environment emulation for VLSI designs: a low cost platform based on xilinx FPGA's

As technology shrinks, critical industral applications have to be designed with special care. VLSI circuits become more sensitive to ambient radiation: it affects to the internal structures, combinational or sequential elements. The effects, known as Single Event Effects (SEEs), are modeled as spontaneous logical changes in a running netlist. They can be mitigated at netlist design level by means of inserting massive redundancy logic in the IC memory elements, as well as designing robust deadlock-free state machines. Current techniques for the analysis and verification of the protection logic for VLSI are inefficient and expensive, lacking either speed or analysis. This paper presents the FT-UNSHADES system. This system is a low cost emulator focused on bit-flip insertion and SEE analysis at hardware speed, based on a Xilinx Virtex-II. Radiation tests are emulated in a highly controlled process, using a non-intrusive method. As a result the system can insert and analyse at least 80K faults per hour in a system with 2 million test vectors